The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
For example, as the critical dimension (CD) of feature is scaled down, the feature may have a relatively high aspect ratio (the ratio of the height vs. width of the feature). When this high aspect ratio reaches a critical value, the feature may actually collapse or fall down during the fabrication process. Accordingly, what is needed is a method for preventing this from happening.